飲料自動(dòng)售賣機(jī)設(shè)計(jì)含開題及8張CAD圖
飲料自動(dòng)售賣機(jī)設(shè)計(jì)含開題及8張CAD圖,飲料,自動(dòng),售賣,設(shè)計(jì),開題,cad
譯文報(bào)告用紙
AT89S51是美國ATMEL公司生產(chǎn)的一款高性能、低功耗的CMOS8位單片機(jī)，片內(nèi)的Flash只讀程序存儲(chǔ)器容量為4 bytes，器件采用ATMEL公司的高密度、非易失性存儲(chǔ)技術(shù)生產(chǎn)，能夠兼容8051指令系統(tǒng)和引腳。它匯集Flash程序存儲(chǔ)器既可在線編程又能用傳統(tǒng)的方式編程及通用8位微處理器于單片機(jī)芯片中。ATMEL公司功能強(qiáng)大、價(jià)格低廉的AT89S51單片機(jī)可為您提供許多高性價(jià)比的應(yīng)用場合，可靈活應(yīng)用于各種控制領(lǐng)域。
主要性能參數(shù)：
u 與MCS-51產(chǎn)品指令完全兼容
u 4K字節(jié)在線系統(tǒng)編程（ISP）Flash閃存
u 1000次擦寫周期
u 4.0-5.5V的工作電壓范圍
u 全靜態(tài)工作模式：0HZ-33MHZ
u 三級(jí)程序加密鎖
u 128 x 8字節(jié)內(nèi)部RAM
u 32個(gè)可編程I/O接口
u 2個(gè)16位置定時(shí)/計(jì)數(shù)器
u 6個(gè)中斷源
u 全雙工串行UART通道
u 低功耗空閑和掉電模式
u 中斷可從空閑模式喚醒系統(tǒng)
u 看門狗（WRT）及雙數(shù)據(jù)指針
u 掉電標(biāo)識(shí)和快速編輯特性
u 靈活的在線系統(tǒng)編程
功能特性概述：
AT89S51提供以下標(biāo)準(zhǔn)功能：4K字節(jié)Flash閃速存儲(chǔ)器，128字節(jié)內(nèi)部RAM，32個(gè)I/O口線，看門狗（WTR），兩個(gè)數(shù)據(jù)指針，兩個(gè)16位定時(shí)/計(jì)數(shù)器，一個(gè)5向量兩級(jí)中斷結(jié)構(gòu)，一個(gè)全雙工串行通信口，片內(nèi)振蕩器及時(shí)鐘電路。同時(shí)AT89S51可降至0HZ的靜態(tài)邏輯操作，并支持兩種軟件可選的節(jié)電工作模式?？臻e方式停止CPU的運(yùn)作，但允許RAM、定時(shí)/計(jì)數(shù)器、串行通信口及中斷系統(tǒng)繼續(xù)工作。掉電方式保存RAM中的內(nèi)容，但振蕩器停止工作并禁止其他一切部件工作，直到下一個(gè)硬件復(fù)位。
引腳功能說明：
VCC：電源電壓
GND：接地端
P0口：P0口是一組8位開路型漏極雙向I/O口。作為輸出口用時(shí)，每位能驅(qū)動(dòng)8個(gè)TTL邏輯門電路，對(duì)端口寫 “1”可作為高阻抗輸入端用。
在訪問外部數(shù)據(jù)存儲(chǔ)器或者程序存儲(chǔ)器時(shí)，這組端口分時(shí)轉(zhuǎn)換地址的低8位和數(shù)據(jù)總線復(fù)用，訪問期間內(nèi)部上拉電阻被激活。
在Flash編程時(shí)P0口接收指令字節(jié)，而在程序校驗(yàn)時(shí)輸出指令字節(jié)并要求外接上拉電阻。
P1口：P1口時(shí)一個(gè)帶內(nèi)部上拉電阻的8位雙向I/O口，P1的輸出緩沖級(jí)（吸收或輸出電流）4個(gè)TTL邏輯門電路。對(duì)端口寫“1”，通過內(nèi)部上拉電阻把端口拉到高電平，此時(shí)可以作為輸入口。因?yàn)榇嬖趦?nèi)部上拉電阻，P1口作為輸入口使用時(shí)，某個(gè)引腳被外部信號(hào)拉到低電平會(huì)輸出一個(gè)電流IIL_
Flash編程和編程校驗(yàn)期間，P1接收低8位地址。
P2口：P2時(shí)一個(gè)帶內(nèi)部上拉電阻的8位雙向I/O口，P2的輸出緩沖級(jí)可驅(qū)動(dòng)（吸收或輸出電流）4個(gè)TTL邏輯門電路。對(duì)端口寫“1”，通過內(nèi)部的上拉電阻，某個(gè)引腳被外部信號(hào)拉低時(shí)會(huì)輸出一個(gè)電路。
在訪問外部程序存儲(chǔ)器或者16位地址的外部數(shù)據(jù)存儲(chǔ)器（例如執(zhí)行MOVX @DPTR指令）時(shí)，P2口送出高8位地址數(shù)據(jù)。在訪問8位地址的外部數(shù)據(jù)存儲(chǔ)器（如執(zhí)行MOVX @Rｉ指令）時(shí)，P2口線上的內(nèi)容（也即特殊功能寄存器（SFR）區(qū)中P2寄存器的內(nèi)容），在整個(gè)訪問期間不會(huì)改變。
Flash編程或者校驗(yàn)時(shí)，P2也接收高位地址和其他控制信號(hào)。
P3口：P3口時(shí)一組帶內(nèi)部上拉電阻的8位雙向I/O口。P3口輸出緩沖級(jí)可驅(qū)動(dòng)（吸收或輸出電流）4個(gè)TTL邏輯門電路。對(duì)P3口寫入“1”時(shí)，它們被內(nèi)部上拉電阻拉高并可以作為輸入端口。作為輸入端時(shí)，被外部信號(hào)拉低的P3口將用上拉電阻輸出電流IIL。
P3口除了作為一般的I/O口線外，更重要的用途時(shí)它的第二功能，如下表所示：
P3口還接收一些用于Flash閃速存儲(chǔ)器編程和程序校驗(yàn)的控制信號(hào)。
RST：復(fù)位輸入。當(dāng)振蕩器工作時(shí)，RST引腳出現(xiàn)兩個(gè)機(jī)器周期以上的高電平將使得單片機(jī)復(fù)位。WDT溢出將使得該引腳輸出高電平，設(shè)置SFR AUXR 的DISRTO位（地址8EH）可打開或者關(guān)閉該功能。DISRTO位缺省為RESET輸出高電平打開狀態(tài)。
ALE/：當(dāng)訪問外部程序存儲(chǔ)器或者數(shù)據(jù)存儲(chǔ)器時(shí)，ALE（地址鎖存允許）輸出脈沖用于鎖存地址的低8位字節(jié)。即使不訪問外部存儲(chǔ)器，ALE仍然以時(shí)鐘振蕩頻率的1/6輸出固定的正脈沖信號(hào)，因此它可對(duì)外輸出時(shí)鐘或者用于定時(shí)目的。要注意的是，每當(dāng)訪問外部數(shù)據(jù)存儲(chǔ)器時(shí)將跳過一個(gè)ALE脈沖。
對(duì)Flash存儲(chǔ)器編程期間，該引腳還用于輸入編程脈沖（）。
如有必要，可通過對(duì)特殊功能寄存器（SFR）區(qū)中的8EH單元的D0位置位，可禁止ALE操作。該位置位后只有MOVX和MOVC指令A(yù)LE才會(huì)被激活。此外，該引腳會(huì)被稍微拉高，單元執(zhí)行外部程序時(shí)，應(yīng)設(shè)置ALE無效。
:程序存儲(chǔ)允許（）輸出的時(shí)外部程序存儲(chǔ)器的讀選通信號(hào)，當(dāng)AT89S51由外部程序存儲(chǔ)器取指令（或者數(shù)據(jù)）時(shí)，每個(gè)機(jī)器周期兩次有效，即輸出兩個(gè)脈沖。當(dāng)訪問外部數(shù)據(jù)存儲(chǔ)器時(shí)，沒有兩次有效的信號(hào)。
EA/VPP：外部訪問允許。欲使得CPU僅訪問外部程序存儲(chǔ)器（地址為0000H-FFFFH），EA端必須保持低電平（接地）。需要注意的是，如果加密位LB1被編程，復(fù)位時(shí)內(nèi)部會(huì)鎖存EA端狀態(tài)。
如果EA端時(shí)高電平（接VCC端），CPU則執(zhí)行內(nèi)部程序存儲(chǔ)器中的指令。
Flash存儲(chǔ)器編程時(shí)，該引腳加上+12V的編程電壓VPP。
XTAL1：振蕩器反相放大器及內(nèi)部時(shí)鐘發(fā)生器的輸入端。
XTAL2：振蕩器反相放大器的輸出端。
特殊功能寄存器：
特殊功能寄存器內(nèi)部空間分布如下表所示：
這些地址并沒有全部占用，沒有占用的地址也不可以使用，讀這些地址將會(huì)得到一個(gè)不確定的數(shù)值。而寫這些地址單元也將得不到預(yù)期的結(jié)果。
表1 AT89S51特殊功能寄存器分布圖及復(fù)位值
不要用軟件方式訪問這些未定義的單元，這些單元時(shí)留作以后產(chǎn)品擴(kuò)展之用，復(fù)位后這些新的位將置為0.
中斷寄存器：各個(gè)中斷允許控制位于IE寄存器，5個(gè)中斷源的中斷優(yōu)先級(jí)控制位位于IP寄存器中。
表2 AUXR輔助寄存器
雙時(shí)鐘指針寄存器：
為更加方便地訪問內(nèi)部和外部數(shù)據(jù)存儲(chǔ)器，AT89S51有兩個(gè)16位數(shù)據(jù)指針寄存器：DP0位于SFR（特殊功能寄存器）區(qū)塊中的地址82H、83H和DP1位于地址84H、85H，當(dāng)SFR中的位DPS=0選擇DP0，而當(dāng)DPS=1則選擇DP1。用戶應(yīng)在訪問相應(yīng)的數(shù)據(jù)指針寄存器前初始化DPS。
電源空閑標(biāo)志：電源空閑標(biāo)志(POF)在特殊功能寄存器SFR中PCON的第4位（PCN.4），電源打開時(shí)POF置“1”，它可由軟件設(shè)置睡眠狀態(tài)并不為復(fù)位所影響。
存儲(chǔ)器結(jié)構(gòu)：MCS-51單片機(jī)內(nèi)核采用了程序存儲(chǔ)器和數(shù)據(jù)存儲(chǔ)器空間分開的結(jié)構(gòu)，都具有64KB的外部程序和數(shù)據(jù)的尋址空間。
程序存儲(chǔ)器：如果EA引腳接地（GND），全部程序均執(zhí)行外部存儲(chǔ)器。在AT89S51中，如果EA接到VCC（電源+），程序首先執(zhí)行地址從0000H-0FFFH（4KB）內(nèi)部程序存儲(chǔ)器，再執(zhí)行地址為1000H-FFFFH（60KB）的外部程序存儲(chǔ)器。
數(shù)據(jù)存儲(chǔ)器：AT89S51有128字節(jié)的內(nèi)部RAM，這128字節(jié)可利用直接或者間接尋址方式進(jìn)行訪問，堆棧操作可以利用間接尋址方式進(jìn)行，128字節(jié)均可設(shè)置位堆棧區(qū)空間。
看門狗定時(shí)器（WDT）：WDT為了解決CPU程序運(yùn)行時(shí)可能進(jìn)入混亂或者死循環(huán)而設(shè)置，它由一個(gè)14Bit計(jì)數(shù)器和看門狗復(fù)位SFR（WDTRST）構(gòu)成。外部復(fù)位時(shí)，WDT默認(rèn)為關(guān)閉狀態(tài)，要打開WDT，用戶必須按順序把01EH和0E1H寫到WDTRST寄存器（SFR地址為0A6H），一旦啟動(dòng)了WDT，它會(huì)隨晶體振蕩器在每個(gè)機(jī)器周期計(jì)數(shù)，除硬件復(fù)位或WDT溢出復(fù)位外沒有其他方法關(guān)閉WDT，當(dāng)WDT溢出，將使RST引腳輸出高電平的復(fù)位脈沖。
使用看門狗（WDT）：打開WDT需按次序?qū)?1EH和0E1H到WDTRST寄存器（SFR的地址為0A6H），當(dāng)WDT打開后，需要一定的時(shí)間寫01EH和0E1H到WDTRST寄存器以避免WDT技術(shù)溢出。14位WDT計(jì)數(shù)器計(jì)數(shù)達(dá)到3FFFFH，WDT將溢出并使得器件復(fù)位。WDT打開時(shí)，它會(huì)隨著晶體振蕩器在每個(gè)機(jī)器周期計(jì)數(shù)，這意味著用戶必須在小于每個(gè)3FFFH機(jī)器周期內(nèi)復(fù)位WDT，也即寫01EH和0E1H到WDTRST寄存器。WDTRST是只寫寄存器，WDT計(jì)數(shù)器既不可以讀也不可以寫，當(dāng)WDT溢出時(shí)，通常將使得RST引腳輸出高電平的復(fù)位脈沖。復(fù)位脈沖持續(xù)時(shí)間為98xTOSC，而TOSC=1/FOSC（晶體振蕩頻率）。為使得WDT工作最優(yōu)化，必須在合適的程序代碼時(shí)間段周期地復(fù)位WDT防止WDT溢出。
掉電和空閑時(shí)的WDT：掉電時(shí)期，晶體振蕩停止，WDT也停止。掉電模式下，用戶不能再復(fù)位WDT。有兩種方法可以退掉掉電模式：硬件復(fù)位或通過激活外部中斷。當(dāng)硬件復(fù)位退出電模式時(shí)，處理WDT可像通常的上電復(fù)位一樣。當(dāng)由中斷退出掉電模式則有所不同，中斷低電平狀態(tài)持續(xù)到晶體振蕩穩(wěn)定，當(dāng)中斷電平變?yōu)楦呒错憫?yīng)中斷服務(wù)。位防止中斷誤復(fù)位，當(dāng)器件復(fù)位，中斷引腳為低時(shí)，WDT并未開始給計(jì)數(shù)，直到中斷引腳為高為止。這為在掉電模式下的中斷執(zhí)行中斷服務(wù)程序而設(shè)置。
為保證WDT在退出掉電模式時(shí)極端情況下不溢出，最好在進(jìn)入掉電模式前復(fù)位WDT。
在進(jìn)入空閑模式前，WDT打開時(shí)WDT是否計(jì)數(shù)由SFR中的AUXR的WDIDLE位決定IDLE期間（位WDIDLE=0）默認(rèn)狀態(tài)是繼續(xù)計(jì)數(shù)。為防止AT89S51從空閑模式中復(fù)位，用戶應(yīng)周期性設(shè)置定時(shí)器，重新進(jìn)入空閑模式。、
當(dāng)WDIDLE被復(fù)位，在空閑模式中WDT將停止計(jì)數(shù)，直到從空閑（IDLE）模式中重新開始計(jì)數(shù)。
UART一通用異步通信口：AT85S51的UART操作與AT89C51一樣，有關(guān)更詳細(xì)的資料請(qǐng)參考ATMEL公司的網(wǎng)站（www.atmel.com）,從主頁選擇“products”-----“8051-Architecture Flash Microcontroller”-----“product Overview”。
定時(shí)器0和定時(shí)器1：AT89S51的定時(shí)器0和定時(shí)器1操作于ATC51一樣，有關(guān)更詳細(xì)的資料請(qǐng)參考ATMEL公司的網(wǎng)站（www.atmel.com），從主頁選擇“Products”——“8951-Architecture Flash Microcontroller”——“Product Overview”。
中斷：AT89s51共有5個(gè)中斷向量：兩個(gè)外部中斷（INT0和INT1），2個(gè)定時(shí)中斷（Timer0和Timer1）和一個(gè)串行中斷。這些中斷如圖1.
這些中斷源各自的禁止和使能位參見特殊功能寄存器的IE。IE也包括總中斷控制位EA，EA清零將關(guān)閉所有中斷。
值得注意的時(shí)表4中的IE.6和IE.5沒有定義，用戶不用訪問這些位它被保留為以后的AT89產(chǎn)品作為擴(kuò)展之用。
定時(shí)器0和定時(shí)器1的中斷標(biāo)志TF0和TF1，它時(shí)定時(shí)器溢出時(shí)候的S5P2時(shí)序周期被置位，該標(biāo)志保留到下個(gè)時(shí)序周期。
表4：中斷控制寄存器
圖1：中斷源方框圖
晶體振蕩器的特性：
AT89S51中由一個(gè)用于構(gòu)成內(nèi)部振蕩器的高增益反相放大器，引腳XTAL1和XTAL2分別時(shí)該放大器的輸入端和輸出端。這個(gè)放大器與作為反饋元件的片外石英晶體或陶瓷振蕩器一起構(gòu)成自激振蕩器，振蕩電路參見圖5.
外接石英晶體（或陶瓷振蕩器）及電容C1、C2接在放大器的反饋回路中構(gòu)成并聯(lián)振蕩電路。對(duì)外接電容C1、C2雖然沒有十分嚴(yán)格的要求，但電容量的大小會(huì)輕微影響振蕩頻率的高低、振蕩器工作的穩(wěn)定性、起振的難易程度及溫度的穩(wěn)定性如果使用石英晶體，我們推薦使用30pF+10F，而如果使用陶瓷諧振器建議選擇40pF+10F。
用戶也可以采用外部時(shí)鐘。采用外部時(shí)鐘的電路如圖5右圖所示。這種情況下，外部時(shí)鐘脈沖接到XTAL1端，即內(nèi)部時(shí)鐘發(fā)生器的輸入端，XTAL2懸空。
由于外部時(shí)鐘信號(hào)時(shí)通過一個(gè)2分頻觸發(fā)器后作為內(nèi)部時(shí)鐘信號(hào)的，所以對(duì)外部時(shí)鐘信號(hào)的占空比沒有特殊要求，但最小高電平持續(xù)時(shí)間和最大的低電平持續(xù)時(shí)間應(yīng)符合產(chǎn)品計(jì)數(shù)條件的要求。
圖2 晶體接線圖和外接時(shí)鐘線路圖：
空閑節(jié)電模式：在空閑工作模式狀態(tài)，CPU保持睡眠狀態(tài)而所有片內(nèi)的外設(shè)仍然保持激活狀態(tài)，這種方式由軟件產(chǎn)生，片內(nèi)RAM和所有特殊功能寄存器的內(nèi)容保持不變?？臻e模式可由任何允許的中斷請(qǐng)求或硬件復(fù)位終止。
需要注意的是，當(dāng)由硬件復(fù)位來終止空閑模式時(shí)，CPU通常是從激活空閑模式那條指令的下一條指令開始繼續(xù)執(zhí)行程序的，要完成內(nèi)部復(fù)位操作，硬件復(fù)位脈沖要保持兩個(gè)機(jī)器周期（24個(gè)時(shí)鐘周期）有效，在這種情況下，內(nèi)部禁止CPU訪問片內(nèi)RAM，而允許訪問其他端口。為了避免在復(fù)位結(jié)束時(shí)可能對(duì)端口產(chǎn)生意外寫入，激活空閑模式的那條指令后一條指令不應(yīng)是一條對(duì)端口或外部存儲(chǔ)器的寫入指令。
掉電模式：在掉電模式下，振蕩器停止工作，進(jìn)如掉電模式的指令時(shí)最后一條被執(zhí)行的指令，片內(nèi)RAM和特殊功能寄存器的內(nèi)容在終止掉電模式前被凍結(jié)。退出掉電模式的方法時(shí)硬件復(fù)位或由處于使能狀態(tài)的外中斷INT0和INT1激活。復(fù)位后將重新定義全部的特殊功能寄存器但不改變RAM中的內(nèi)容，在Vcc恢復(fù)到正常工作電平前，復(fù)位應(yīng)無效，且必須保持一定時(shí)間按以使振蕩器重啟并穩(wěn)定工作。
表5 空閑和掉電期間外部引腳狀態(tài)：
程序存儲(chǔ)器的加密：AT89S51可使用對(duì)芯片上的3個(gè)加密位LB1、LB2、LB3進(jìn)行編程（P）或不編程（U）來得到如下表所示的功能：
加密位保護(hù)功能表： 注：表中的U——表示未編程，P——表示編程
當(dāng)加密位LB1被編程時(shí)，在復(fù)位期間，EA端的邏輯電平被采樣并鎖存，如果單片機(jī)上電后一直沒有復(fù)位，則鎖存其來的初始值時(shí)一個(gè)隨機(jī)數(shù)，且這個(gè)隨機(jī)數(shù)會(huì)一直保存到真正復(fù)位為止。為使單片機(jī)能正常工作，被鎖存的EA電平值必須與該引腳當(dāng)前的邏輯電平一致。此外，加密位只能通過整片擦除的方法清除。
Flash閃速存儲(chǔ)器的并行編程：AT89S51單片機(jī)內(nèi)部有4k字節(jié)的可快速編程的Flash存儲(chǔ)陣列。編程方法可通過傳統(tǒng)的EPROM編程器使用高電壓（+12v）和協(xié)調(diào)的控制信號(hào)進(jìn)行編程。
AT89S51的代碼是逐一字節(jié)進(jìn)行編程的。
編程方法：編程前，須按照編程模式表和圖13、圖14所示設(shè)置好地址、數(shù)據(jù)及控制信號(hào)，AT89S51編程方法如下：
1. 在地址線上加上要編程單元的地址信號(hào)
2. 在數(shù)據(jù)線上加上要寫入的數(shù)據(jù)字節(jié)
3. 激活相應(yīng)的控制信號(hào)
4. 將EA/Vpp端加上+12編程電壓。
5. 每對(duì)Flash存儲(chǔ)陣列寫入一個(gè)字節(jié)或每寫入一個(gè)程序加密位，加上一個(gè)ALE/編程脈沖。每個(gè)字節(jié)寫入周期是自身定時(shí)的，大多數(shù)約為50uS。改變編程單元的地址和寫入的數(shù)據(jù)，重復(fù)1——5步驟，直到全部文件編程結(jié)束。
數(shù)據(jù)查詢：AT89S51單片機(jī)用數(shù)據(jù)查詢方式來檢測(cè)一個(gè)寫周期是否結(jié)束，在一個(gè)寫周期中，如需讀取最后寫入的哪個(gè)字節(jié)，則讀出的數(shù)據(jù)最高位（P0.7）是原來寫入字節(jié)最高位的反碼。寫周期完成后，有效的數(shù)據(jù)就會(huì)出現(xiàn)在所有輸出端上，此時(shí)，可進(jìn)入下一個(gè)字節(jié)的寫周期，寫周期開始后，可在任意時(shí)刻進(jìn)行數(shù)據(jù)查詢。
Ready/:字節(jié)編程的進(jìn)度要通過“RDY/BSY”輸出信號(hào)監(jiān)測(cè)，編程期間，ALE變?yōu)楦唠娖健癏”后P3.0端電平被拉低，表示正在編程狀態(tài)（忙狀態(tài)）。編程完成后，可在任意時(shí)刻進(jìn)行數(shù)據(jù)查詢。
程序校驗(yàn)：如果加密位LB1、LB2沒有進(jìn)行編程，則代碼數(shù)據(jù)可通過地址和數(shù)據(jù)線讀回原編寫的數(shù)據(jù)，各加密位也可通過直接回讀進(jìn)行校驗(yàn)。
讀片內(nèi)簽名字節(jié)：AT89S51單片機(jī)內(nèi)由3個(gè)簽名字節(jié)，地址為000H、100H和200H。用于聲明該器件的廠商和型號(hào)等信息，讀簽名字節(jié)的過程和正常校驗(yàn)相仿，只需將P3.6和P3.7保持低電平，返回值意義如下：
（000H）=1EH 聲明產(chǎn)品由ATMEL公司制造。
（100H）=51H聲明為AT89S51單片機(jī)
（200H）=06H
芯片的擦除：在并行編程模式，利用控制信號(hào)的正確組合并保持ALE/引腳200ns——500ns的低電平脈沖寬度即可完成擦除操作。
在串行編程模式，芯片擦除操作是利用擦除指令進(jìn)行的。在這種方式，擦除周期時(shí)自身定時(shí)的，大約位500MS。
擦除期間，用串行方式讀任何地址數(shù)據(jù)，返回值均為00H。
Flash閃速存儲(chǔ)器的串行編程：將RST接到Vcc，程序代碼存儲(chǔ)器陣列可通過串行ISP接口進(jìn)行編程，串行接口包含SCK線、MOSI（輸出）線。將RST拉高后，在其他操作前必須發(fā)出編程使能指令，編程前需要將芯片擦除。
芯片擦除則將存儲(chǔ)代碼陣列全寫位FFH。
外部系統(tǒng)時(shí)鐘信號(hào)需接到XTAL端或者在XTAL1和XTAL2接上晶體振蕩器。最高的串行時(shí)鐘（SCK）不超過1/16晶體時(shí)鐘，當(dāng)晶體為33MHZ時(shí)，最大SCK頻率為2MHZ。
Flash閃速存儲(chǔ)器的串行編程方法：對(duì)AT89S51的串行編程次序推薦使用以下方法：
1. 上電次序：將電源家在Vcc和GND引腳，RST置為”H”，如果XTAL1和XTAL2接上晶體或者在XTAL1接上3-33MHZ的時(shí)鐘頻率，等候10MS。
2. 將編程使能指令發(fā)送到MOSI(Pin1.5)，編程時(shí)鐘接至SCK（pin1.7），次頻率需小于晶體時(shí)鐘頻率的1/16.
3. 代碼陣列的編程可選字節(jié)模式或者頁模式。寫周期時(shí)自身定時(shí)的，一般不大于0.5ms（5v電壓時(shí)）。
4. 任意代碼單元均可MISO（pin1.6）和讀指令選擇相應(yīng)的地址回讀數(shù)據(jù)進(jìn)行校驗(yàn)。
5. 編程結(jié)束應(yīng)將RST置為“L”以結(jié)束操作。
6. 斷電次序：如果需要的話，按這個(gè)方法斷電，加入沒有使用晶體，將XTAL置為低，RST置為低，關(guān)斷Vcc。
數(shù)據(jù)校驗(yàn)：數(shù)據(jù)校驗(yàn)也可在串行模式下進(jìn)行，在這個(gè)模式，在一個(gè)寫周期中，通過輸出引腳MISO串行回讀一個(gè)字節(jié)數(shù)據(jù)的最高位將為最后寫入字節(jié)的反碼。
串行指令編程設(shè)置：串行編程指令設(shè)置為一個(gè)4字節(jié)的協(xié)議，參見表8.
并行編程接口：采用控制信號(hào)的正確組合可對(duì)Flash閃速存儲(chǔ)陣列中的每一代碼字節(jié)進(jìn)行寫入和存儲(chǔ)器的整片擦除，寫操作周期是自身定時(shí)的，初始化后它將會(huì)自動(dòng)定時(shí)到操作完成。
更多的有關(guān)ATMEL系列單片機(jī)的編程計(jì)數(shù)請(qǐng)聯(lián)系相應(yīng)的編程器供應(yīng)商以獲取最新的軟件版本。
表7 Flash編程模式：
注：1.芯片擦除每一脈沖為200ns—500ns。
2.寫代碼數(shù)據(jù)每一脈沖為200ns—500ns。
3.寫加密位每一脈沖為200ns—500ns。
4.編程期間P3.0引腳輸出RDY/信號(hào)。
5.“X”不需要理會(huì)。
圖4 Flash存儲(chǔ)器編程（并口模式） 圖5 Flash存儲(chǔ)器校驗(yàn)（并口模式）
Flash編程和校驗(yàn)特性（并行模式）：
圖6 Flash編程和校驗(yàn)波形（并行模式）
Flash存儲(chǔ)器的串行下載：
Flash編程和校驗(yàn)波形（串行模式）：
表8 串行編程指令：
注：1.當(dāng)LB3和LB4加密位已編程時(shí)則不可讀簽名字節(jié)。
2.B1=0 B2=0,方式1，無加密保護(hù)
B1=0 B2=1,方式2，加密位LB1 各個(gè)加密位在方式4執(zhí)行前需按順序逐一操作
B1=1 B2=0,方式3，加密位LB2
B1=1 B2=1,方式4，加密位LB3
復(fù)位信號(hào)為”H”后，建立數(shù)據(jù)前使SCK為低電平至少64個(gè)系統(tǒng)時(shí)鐘周期，復(fù)位脈沖時(shí)必須的。SCK時(shí)鐘頻率不得大于XTAL1時(shí)鐘的1/16.
在頁讀/寫模式，數(shù)據(jù)總是從地址00開始直到255.命令字節(jié)后緊跟著高4位地址，全部數(shù)據(jù)單元256字節(jié)會(huì)逐一進(jìn)行讀/寫，此時(shí)下個(gè)指令將準(zhǔn)備譯碼。
串行編程特性：
圖9 串行編程時(shí)序
極限參數(shù)：
注：這些參數(shù)是器件的極限參數(shù)，使用條件必須在上述列表范圍以內(nèi)，如果超出上述條件，器件就不能得到安全保證甚至可能造成永久性破壞。
DC參數(shù)：
注：以下參數(shù)測(cè)試條件：在TA=40°C—85°C，Vcc=4.0v—5.5v
注： 1.在穩(wěn)定狀態(tài)（無輸出）條件下，Iol有以下限制：每一引腳最大Iol為10mA，每一8位端口p0為26mA，P1、P2、P3為15mA。 全部輸出引腳最大Iol為71mA。
2.掉電模式的最小Vcc為2v。
AC特性：
在以下工作條件測(cè)得：P0、ALE/PROG和PSEN負(fù)載容抗為100pF，其他端口負(fù)載容抗為80PF。
外部程序和數(shù)據(jù)存儲(chǔ)器特性：
外部程序存儲(chǔ)器讀周期：
外部數(shù)據(jù)存儲(chǔ)器讀周期：
外部程序存儲(chǔ)器寫周期：
外部數(shù)據(jù)存儲(chǔ)器寫周期：
外部時(shí)鐘驅(qū)動(dòng)時(shí)序：
串行口時(shí)序：
在Vcc=4.0v—5.5v，負(fù)載電容為80pF條件下：
上位寄存器時(shí)序波形：
AC測(cè)試輸入/輸出波形;
注：AC輸入測(cè)試在Vcc-0.5v邏輯1及0.45v為邏輯0，時(shí)序測(cè)試在VIH為最小是和VIL為最大測(cè)量。
浮空波形：
注：在浮空狀態(tài)，端口引腳在負(fù)載出現(xiàn)100mv電壓變化時(shí)即為浮空，也即當(dāng)一個(gè)端口電壓從VOH到VOL變化時(shí)出現(xiàn)100mv電壓時(shí)浮空狀態(tài)。
產(chǎn)品信息：
封裝形式：
[1] S. P. Amarasinghe, J. M. Anderson, M. S. Lam, and C.-W.Tseng, “An overview of the SUIF compiler for scalable parallel machines,” Proceedings of the Seventh SIAM Conference onParallel Processing for Scientific Compiler, San Francisco, 1995.
[2] S. Amarasinghe et.al., “Hot compilers for future hot chips,” presented at Hot Chips VII, Stanford, CA, 1995.
[3] D. W. Anderson, F. J. Sparacio, and R. M. Tomasulo, “The IBM System/360 model 91: Machine philosophy and instruction-handling,” IBM Journal of Research and Development, vol. 11, pp. 8–24, 1967.
22
本科生畢業(yè)論文（設(shè)計(jì)）
英文原文
原文出處：
DOUGLASLP.VHDL：programming by example[M]．New York：McGraw—Hill Professional2002．
FOREWORD
VHDL has been at the heart of electronic design productivity since initial ratification by the IEEE in 1987. For almost 15 years the electronic design automation industry has expanded the use of VHDL from initial concept of design documentation, to design implementation and func tional verification. It can be said that VHDL fueled modern synthesis technology and enabled the development of ASIC semiconductor compa nies. This book has served as the authoritative source of practical information on the use of VHDL for users of the language around the world.
The use of VHDL has evolved and its importance increased as semi conductor devices dimensions have shrunk. Not more than 10 years ago it was common to mix designs described with schematics and VHDL. But as design complexity grew, the industry abandoned schematics in favor of the hardware description language only. The successive revisions of this book have always kept pace with the industry’s evolving use of VHDL.
The fact that VHDL is adaptable is a tribute to its architecture. The industry has seen the use of VHDL’s package structure to allow design ers, electronic design automation companies and the semiconductor indus try to experiment with new language concepts to ensure good design tool and data interoperability. When the associated data types found in the IEEE 1164 standard were ratified, it meant that design data interoper ability was possible.
All of this was facilitated by industry backing in a consortium of systems, electronic design automation and semiconductor companies now known as Accellera.
And when the ASIC industry needed a standard way to convey gate-level design data and timing information in VHDL, one of Accellera’s progenitors (VHDL International) sponsored the IEEE VHDL team to build a companion standard. The IEEE 1076.4 VITAL (VHDL Initiative Towards ASIC Libraries) was created and ratified as offers designers a single language flow from concept to gate-level signoff.
In the late ’90s, the Verilog HDL and VHDL industry standards teams collaborated on the use of a common timing data such as IEEE 1497 SDF, set register transfer level (RTL) standards and more to improve design methodologies and the external connections provided to the hardware description languages.
But from the beginning, the leadership of the VHDL community has assured open and internationally accredited standards for the electronic design engineering community. The legacy of this team’s work continues to benefit the design community today as the benchmark by which one measures openness.
The design community continues to see benefits as the electronic design automation community continues to find new algorithms to work from VHDL design descriptions and related standards to again push designer productivity.And, as a new generation of designers of programmable logic devices move to the use of hardware description languages as the basis of their design methodology, there will be substantial growth in the number of VHDL users.
This new generation of electronic designers, along with the current designers of complex systems and ASICs, will find this book invaluable . Updated with current ue of the standard, all will benefit from the years of use that have made the VHDL language the underpinning of successful electronic design.
Introduction to VHDL
The VHSIC Hardware Description Language is an industry standard language used to describe hardware from the abstract to the concrete level. VHDL resulted from work done in the ’70s and early ’80s by the U.S. Department of Defense. Its roots are in the ADA language, as will be seen by the overall structure of VHDL as well as other VHDL statements.
VHDL usage has risen rapidly since its inception and is used by literally tens of thousands of engineers around the globe to create sophisticated electronic products. This chapter will start the process of easing the reader into the complexities of VHDL. VHDL is a powerful language with numerous language constructs that are capable of describing very complex behavior. Learning all the features of VHDL is not a simple task. Complex features will be introduced in a simple form and then more complex usage will be described.
In 1986, VHDL was proposed as an IEEE standard. It went through a number of revisions and changes until it was adopted as the IEEE 1076 standard in December 1987. The IEEE 1076-1987 standard VHDL is the VHDL used in this book.(Appendix D contains a brief description of VHDL 1076-1993.) All the examples have been described in IEEE 1076 VHDL, and compiled and simulated with the VHDL simulation environment from Model Technology Inc.
VHDL Terms
Before we go any further, let’s define some of the terms that we use throughout the book. These are the basic VHDL building blocks that are used in almost every description, along with some terms that are redefined in VHDL to mean something different to the average designer.
Entity. All designs are expressed in terms of entities. An entity is the most basic building block in a design. The uppermost level of the design is the top-level entity. If the design is hierarchical, then the top-level description will have lowerlevel descriptions contained in it. These lower-level descriptions will be lowerlevel mentities contained in the top-level entity description.
Architecture. All entities that can be simulated have an architecture
description. The architecture describes the behavior of the entity. A single entity can have multiple architectures. One architecture might be behavioral while another might be a structural description of the design.
Configuration. A configuration statement is used to bind a component instance to an entity-architecture pair. A configuration can be considered like a parts list for a design. It describes which behavior to use for each entity, much like a parts list describes which part to use for each part in the design.
Package. A package is a collection of commonly used data types and
subprograms used in a design. Think of a package as a toolbox that contains
tools used to build designs.
Driver. This is a source on a signal. If a signal is driven by two sources, then when both sources are active, the signal will have two drivers.
Bus. The term “bus” usually brings to mind a group of signals or a particular method of communication used in the design of hardware. In VHDL, a bus is a special kind of signal that may have its drivers turned off.
Attribute. An attribute is data that are attached to VHDL objects or predefined data about VHDL objects. Examples are the current drive capability of a buffer or the maximum operating temperature of the device.
Generic. A generic is VHDL’s term for a parameter that passes information to an entity. For instance, if an entity is a gate level model with a rise and a fall delay, values for the rise and fall delays could be passed into the entity with generics.
Process. A process is the basic unit of execution in VHDL. All operations that are performed in a simulation of a VHDL description are broken into single or multiple processes.
Describing Hardware in VHDL
VHDL Descriptions consist of primary design units and secondary design units. The primary design units are the Entity and the Package. The secondary design units are the Architecture and the Package Body. Secondary design units are always related to a primary design unit. Libraries are collections of primary and secondary design units. A typical design usually contains one or more libraries of design units.
Entity
A VHDL entity specifies the name of the entity, the ports of the entity, and entityrelated information. All designs are created using one or more entities. Let’s take a look at a simple entity example:
ENTITY mux IS
PORT ( a, b, c, d : IN BIT;s0, s1 : IN BIT; x, : OUT BIT);
END mux;
The keyword ENTITY signifies that this is the start of an entity statement. In the descriptions shown throughout the book, keywords of the language and types provided with the STANDARD package are shown in ALL CAPITAL letters. For instance, in the preceding example, the keywords are ENTITY, IS, PORT, IN, INOUT, and so on. The standard type provided is BIT. Names of user-created objects such as mux, in the example above, will be shown in lower case.
The name of the entity is mux. The entity has seven ports in the PORT clause. Six ports are of mode INand one port is of mode OUT. The four data input ports (a, b, c, d) are of type BIT. The two multiplexer select inputs, s0 and s1, are also of type BIT. The output port is of type BIT. The entity describes the interface to the outside world. It specifies the number of ports, the direction of the ports, and the type of the ports. A lot more information can be put into the entity than is shown here, but this gives us a foundation upon which we can build more complex examples.
Architectures
The entity describes the interface to the VHDL model. The architecture describes the underlying functionality of the entity and contains the statements that model the behavior of the entity. An architecture is always related to an entity and describes the behavior of that entity. An architecture for the counter device described earlier would look like this:
ARCHITECTURE dataflow OF mux ISSIGNAL select : INTEGER;
BEGIN
select <= 0 WHEN s0 = ‘0’ AND s1 = ‘0’ ELSE1 WHEN s0 = ‘1’ AND s1= ‘0’ ELSE2 WHEN s0 = ‘0’ AND s1 = ‘1’ ELSE3;
x <= a AFTER 0.5 NS WHEN select = 0 ELSEb AFTER 0.5 NS WHEN
select = 1 ELSEc AFTER 0.5 NS WHEN select = 2 ELSEd AFTER 0.5 NS;
END dataflow;
The keyword ARCHITECTURE signifies that this statement describes an
architecture for an entity. The architecture name is dataflow. The entity
the architecture is describing is called mux.
The reason for the connection between the architecture and the entity is that an entity can have multiple architectures describing the behavior of the entity. For instance, one architecture could be a behavioral description, and another could be a structural description.
The textual area between the keyword ARCHITECTURE and the keyword BEGIN is where local signals and components are declared for later use.In this example signal select is declared to be a local signal.
The statement area of the architecture starts with the keyword BEGIN.
All statements between the BEGINand the ENDnetlist statement are called
concurrent statements, because all the statements execute concurrently.
Default Configurations
The simplest form of explicit configuration is the default configuration. This configuration can be used for models that do not contain any blocks or components to configure. The default configuration specifies the configuration name, the entity being configured, and the architecture to be used for the entity. Following is an example of two default configurations shown by configurations big_count and small_count:
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
ENTITY counter IS
PORT(load, clear, clk : IN std_logic;
PORT(data_in : IN INTEGER;
PORT(data_out : OUT INTEGER);
END counter;
ARCHITECTURE count_255 OF counter IS
BEGIN
PROCESS(clk)
VARIABLE count : INTEGER := 0;
BEGIN
IF clear = ‘1’ THEN
count := 0;
ELSIF load = ‘1’ THEN
count := data_in;
ELSE
IF (clk’EVENT) AND (clk = ‘1’) AND
(clk’LAST_VALUE = ‘0’) THEN
IF (count = 255) THEN
count := 0;
ELSE
count := count + 1;
END IF;
END IF;
END IF;
data_out <= count;
END PROCESS;
END count_255;
ARCHITECTURE count_64k OF counter IS
BEGIN
PROCESS(clk)
VARIABLE count : INTEGER := 0;
BEGIN
IF clear = ‘1’ THEN
count := 0;
ELSIF load = ‘1’ THEN
count := data_in;
ELSE
IF (clk’EVENT) AND (clk = ‘1’) AND
(clk’LAST_VALUE = ‘0’) THEN
IF (count = 65535) THEN
count := 0;
ELSE
count := count + 1;
END IF;
END IF;
END IF;
data_out <= count;
END PROCESS;
END count_64k;
CONFIGURATION small_count OF counter IS
FOR count_255
END FOR;
END small_count;
CONFIGURATION big_count OF counter IS
FOR count_64k
END FOR;
END big_count;
This example shows how two different architectures for a counter entity can be configured using two default configurations. The entity for the counter does not specify any bit width for the data to be loaded into the counter or data from the counter. The data type for the input and output data is INTEGER.With a data type of integer, multiple types of counters can be supported up to the integer representation limit of the host computer for the VHDL simulator.
The two architectures of entity counter specify two different-sized counters that can be used for the entity. The first architecture, count_255, specifies an 8-bit counter. The second architecture, count_64k, specifies a 16-bit counter. The architectures specify a synchronous counter with a synchronous load and clear. All operations for the device occur with respect to the clock.
Each of the two configurations for the entity specifies a different architecture for the counter entity. Let’s examine the first configuration in more detail. The configuration design unit begins with the keyword CONFIGURATION and is followed by the name of the configuration. In this example, the name of the configuration is small_count. The keyword OF precedes the name of the entity BEGIN configured (counter). The next line of the configuration starts the block configuration section. The keyword FOR is followed by a name of the architecture to use for the entity being configured or the name of the block of the architecture that will be configured. Any component or block configuration information then exists
between the FOR ARCHITECTURE clause and the matching END FOR.
In this architecture, there are no blocks or components to configure; therefore, the block configuration area from the FOR clause to the END FOR clause is empty, and the default is used. The configuration is called the default configuration, because the default is used for all objects in the configuration.
The first configuration is called small_count and binds architecture count_255 with entity counter to form a simulatable object. The second configuration binds architecture count_64k with entity counter and forms a simulatable object called big_count.
第 9 頁 共 9 頁
收藏