第24頁 計(jì)算機(jī)組成原理課程設(shè)計(jì)說明書題 目： 設(shè)計(jì)一臺(tái)嵌入式CISC模型計(jì)算機(jī) 院 （系）： 計(jì)算機(jī)科學(xué)與工程學(xué)院 專 業(yè)： 網(wǎng)絡(luò)工程 學(xué)生姓名： 唐波 學(xué) 號(hào)： 1100380219 指導(dǎo)教師： 陳智勇 一、課設(shè)題目：設(shè)計(jì)一臺(tái)嵌入式CISC模型計(jì)算機(jī)（采用定長(zhǎng)CPU周期、聯(lián)合控制方式），并運(yùn)行能完成一定功能的機(jī)器語言程序進(jìn)行驗(yàn)證，實(shí)現(xiàn)方法可從以下4類中任選一個(gè)： 連續(xù)輸入5個(gè)有符號(hào)整數(shù)（8位二進(jìn)制補(bǔ)碼表示，用十六進(jìn)制數(shù)輸入），求最小的負(fù)數(shù)的絕對(duì)值并輸出顯示。 說明：5個(gè)有符號(hào)數(shù)從外部輸入； 一定要使用符號(hào)標(biāo)志位（比如說SF），并且要使用為負(fù)的時(shí)候轉(zhuǎn)移（比如JS）或不為負(fù)的時(shí)候轉(zhuǎn)移（比如JNS）指令。二CISC模型機(jī)系統(tǒng)總體設(shè)計(jì)三操作控制器的邏輯框圖指令寄存器IR操作碼微地址寄存器地址譯碼控制存儲(chǔ)器地址轉(zhuǎn)移邏輯狀態(tài)條件微命令寄存器P字段操作控制字段微命令信號(hào)說明：在T4內(nèi)形成微指令的微地址，并訪問控制存儲(chǔ)器，在T2的上邊沿到來時(shí)，將讀出的微指令打入微指令寄存器，即圖中的微命令寄存器和微地址寄存器。四模型機(jī)的指令系統(tǒng)和所有指令的指令格式由此可見，本模型機(jī)中的指令系統(tǒng)中共有8條基本指令，下表9列出了每條指令的格式、匯編符號(hào)和指令功能。指令助記符指令格式功能15-1211 109 87-0IN1 Rd0101Rd(Rd)+1Rd，鎖存標(biāo)志位MOV Rd,im0001Rdim立即數(shù)RdCMP Rs,Rd0011RsRdRs,Rd比較，INC Rd0010Rd輸入設(shè)備RdJNS addr0100addr若大于，則addrPCJMP addr0110addraddrPCOUT1 Rs1001Rs(Rs)輸出設(shè)備MOV1 Rs,Rd1000RsRd(Rs)RdNOT Rd0111RdData取反指令格式：（1）I/O指令（單字節(jié)）I說明：對(duì)Rs和Rd的規(guī)定：Rs或Rd選定的寄存器0 0R00 1R11 0R2 1 1R3 五所有機(jī)器指令的微程序流程圖00PCABUS（I）RD ROMIBUSIRPC+100P(1)MOV1OUT1IN1MOVNOTJMPJNSCMPINC030209080107O60504RsX-XRs鎖存CF，ZFRsXRdY鎖存CF，ZFRdYY+1Rd鎖存CF，ZFIR（I）RdRsLEDRsXXRdIR（A）PCSWRd200000P(2)00000000000000 CF=1ZF=1CF=0ZF=010ROMBUSBUSPC0000設(shè)計(jì)操作控制器單元（即微程序控制器） （1）設(shè)計(jì)微指令格式和微指令代碼表CISC模型機(jī)系統(tǒng)使用的微指令采用全水平型微指令，字長(zhǎng)為25位，其中微命令字段為17位，P字段為2位，后繼微地址為6位，其格式如下： 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0LOAD LDPC LDAR LDIR LDRi RD_B RS_B S2 S1 S0 ALU_B SW_B LED_B RD_D CS_D RAM_B CS_I ADDR_B P1 P2 后繼微地址由微指令格式和微程序流程圖編寫的微指令代碼表如下所示，在微指令的代碼表中微命令字段從左邊到右代表的微命令信號(hào)依次為：LOAD LDPC LDAR LDIR LDRi RD_B RS_B S2 S1 S0 ALU_B SW_B LED_B RD_D CS_D RAM_B CS_I ADDR_B微地址微命令字段P1P2后繼微地址00110100100011111101100000100110001010001111111000000000021000111010011111110000000103100001100111111111000000000410000010001101111101000011051000101000101111110000010006010000100011111110001000000710001111000111111100000000081000101101011111110001001009100000000011011111000101001001000010001111111000000000 （2）設(shè)計(jì)地址轉(zhuǎn)移邏輯電路地址轉(zhuǎn)移邏輯電路是根據(jù)微程序流程圖3-2中的棱形框部分及多個(gè)分支微地址，利用微地址寄存器的異步置“1”端，實(shí)現(xiàn)微地址的多路轉(zhuǎn)移。由于微地址寄存器中的觸發(fā)器異步置“1”端低電平有效，與A4A0對(duì)應(yīng)的異步置“1”控制信號(hào)SE5SE1的邏輯表達(dá)式為：（A5的異步置“1”端SE6實(shí)際未使用）SE5= FSP(2)T4SE4=I7P(1)T4SE3=I6P(1)T4SE2=I5P(1)T4SE1=I4P(1)T4六嵌入式CISC模型計(jì)算機(jī)的頂層電路圖CROM:AA;七匯編代碼：MOV R0,00H 功能：將0賦給R0MOV R1,FFH 將FF賦給R1MOV R2,05H 將05賦給R2L0:INC R0 計(jì)數(shù)加1 CMP R0,R2 R0與R2比較，是否輸入五個(gè)數(shù)JNS L3 是跳轉(zhuǎn)L2輸出 IN1 R3 輸入一個(gè)數(shù)到R3CMP R3,R1 R3和R1比較，鎖存CF，ZFJNS L2 跳轉(zhuǎn)L2輸出JMP L1 跳轉(zhuǎn)L1L1:MOV1 R1,R3 （R3）（R1）JMP L0 跳轉(zhuǎn)L0L2: NOT R1 R1取反INC R1 R1加1OUT1 R1 輸出R1 八機(jī)器語言源程序地址（十六進(jìn)制）匯編語言源程序 機(jī)器語言源程序 代碼00 MOV R0,00H 0001 0000 0000 0000 100001 MOV R1,FFH 0001 0001 1111 1111 11FF02 MOV R2,05H 0001 0010 0000 0101 102503 L0:INC R0 0010 0000 0000 0000 2000 04 CMP R0,R2 0011 1000 0000 0000 3800 05 JNS L3 0100 0000 0000 1100400C 06 IN1 R3 0101 0011 0000 0000 5300 07 CMP R3,R1 0011 1101 0000 0000 3D00 08 JNS L2 0100 0000 0000 1010400A09 JMP L1 0110 0000 0000 0011 60030A L1:MOV1 R1,R3 1000 1101 0000 0000 8D000B JMP L0 0110 0000 0000 0011 60030C L2: NOT R1 0111 0001 0000 0000 71000D INC R1 0010 0001 0000 0000 21000E OUT1 R1 1001 0100 0000 0000 9400九機(jī)器語言源程序的功能仿真波形圖及結(jié)果分析1.MOV R0,00H 2.MOV R1,FFH 3.MOV R2,05H 4.CMP R2,R0 5.IN1 R3(F4存到R3)6MOV1 R3,R1(F4存入R1) 7.IN1 R3(02存到R3) 802是大于F4的正數(shù)，不跳到L1存R1，直接跳回L0。9.IN1 R3（F1存到R3)。10F1是小于于F4的負(fù)數(shù)，跳到L1，MOV1 R3,R1(F1存入R1)11FNOT R1， INC R1（F1取反加1存入R1）。 12。OUT1 R1（輸出R1，最終結(jié)果是0F）十故障現(xiàn)象和故障分析故障一：在進(jìn)行仿真的時(shí)候，當(dāng)輸入一個(gè)正數(shù)存進(jìn)R3之后，執(zhí)行CMP R3,R1之后，沒有執(zhí)行JNS L0，而是錯(cuò)將正數(shù)也存入R1。查看之后發(fā)現(xiàn)是ALU里“CMP”運(yùn)算代碼有問題。故障二：計(jì)數(shù)（R0）一直加，到5時(shí)不會(huì)跳轉(zhuǎn)輸出，檢查機(jī)器指令發(fā)現(xiàn)JNS L2的地址寫成了06故障三：，輸出結(jié)果時(shí)，取反都變成FB，檢查很久之后發(fā)現(xiàn)原本應(yīng)該對(duì)AC里的數(shù)取反的，結(jié)果弄成了DR的.故障N:匯編程序出錯(cuò)、連線錯(cuò)誤、微指令錯(cuò)誤、修改器件沒有重新編譯等。十一.心得體會(huì)剛開始去上老師的課時(shí)，聽得一頭霧水，因?yàn)榘l(fā)現(xiàn)好多地方自己同不懂。然后我就去看課本，同時(shí)問老師一些問題，當(dāng)看到其他同學(xué)也問老師問題時(shí)，自己也跑過去湊熱鬧，因?yàn)檫@樣可以了解更多的知識(shí)。直到后來才發(fā)現(xiàn)，原來除了設(shè)計(jì)自己的指令外，我們需要寫MCOMMAND，寫CONTROM來解析我們寫的指令，這或許可以算得上一個(gè)極簡(jiǎn)單的CPU模型了吧。就是有了微程序控制器，計(jì)算機(jī)才認(rèn)識(shí)我們自己設(shè)計(jì)的指令，才知道當(dāng)讀取到什么指令時(shí)該執(zhí)行什么操作。聽得多了，看得多了，就漸漸的明白了一些課設(shè)的相關(guān)知識(shí)，然后畫指令流程圖，設(shè)計(jì)指令，寫程序完成任務(wù)，這些幾乎都是水到渠成的工作了，很多都可以依葫蘆畫瓢來完成。本次課設(shè)，由于匯編學(xué)的很差，期匯編代碼是和班級(jí)同學(xué)的相同，但是自己重新設(shè)計(jì)了指令周期流程圖，經(jīng)過調(diào)試得出的結(jié)果其實(shí)只要把最基本的原理搞明白了，后續(xù)工作開展是非?？斓摹５跊]明白原理前，千萬不要畏懼困難，慢慢的一點(diǎn)一點(diǎn)學(xué)習(xí)，特別是仿真軟件的學(xué)習(xí)和使用，需要花費(fèi)相當(dāng)?shù)臅r(shí)間。只要認(rèn)真了，就有可能實(shí)現(xiàn)。十二.軟件清單AA里的MMM:LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY MMM IS PORT( SE:IN STD_LOGIC; CLK:IN STD_LOGIC; D:IN STD_LOGIC; CLR:IN STD_LOGIC; UA:OUT STD_LOGIC );END MMM;ARCHITECTURE A OF MMM ISBEGIN PROCESS(CLR,SE,CLK) BEGIN IF(CLR=0) THEN UA<=0; ELSIF(SE=0)THEN UA<=1; ELSIF(CLKEVENT AND CLK=1) THEN UA<=D; END IF; END PROCESS;END A;CROM的：ADDRLIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY ADDR IS PORT( I15,I14,I13,I12:IN STD_LOGIC; ZF,CF,T4,P1,P2:IN STD_LOGIC; SE5,SE4,SE3,SE2,SE1,SE0:OUT STD_LOGIC);END ADDR;ARCHITECTURE A OF ADDR ISBEGIN SE5<=1; -預(yù)留給JB或JAE指令使用 SE4<=NOT(NOT ZF AND CF)AND P2 AND T4); SE3<=NOT(I15 AND P1 AND T4); SE2<=NOT(I14 AND P1 AND T4); SE1<=NOT(I13 AND P1 AND T4); SE0<=NOT(I12 AND P1 AND T4);END A;LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY F1 IS PORT( UA5,UA4,UA3,UA2,UA1,UA0: IN STD_LOGIC; D:OUT STD_LOGIC_VECTOR(5 DOWNTO 0);END F1;ARCHITECTURE A OF F1 ISBEGIN D(5)<=UA5; D(4)<=UA4; D(3)<=UA3; D(2)<=UA2; D(1)<=UA1; D(0)<=UA0;END A;LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY F2 IS PORT( D:IN STD_LOGIC_VECTOR(5 DOWNTO 0); UA5,UA4,UA3,UA2,UA1,UA0: OUT STD_LOGIC );END F2;ARCHITECTURE A OF F2 ISBEGIN UA5<=D(5); UA4<=D(4); UA3<=D(3); UA2<=D(2); UA1<=D(1); UA0<=D(0);END A;LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_ARITH.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY CONTROM ISPORT(ADDR: IN STD_LOGIC_VECTOR(5 DOWNTO 0); UA:OUT STD_LOGIC_VECTOR(5 DOWNTO 0); O:OUT STD_LOGIC_VECTOR(19 DOWNTO 0) );END CONTROM;ARCHITECTURE A OF CONTROM ISSIGNAL DATAOUT: STD_LOGIC_VECTOR(25 DOWNTO 0);BEGIN PROCESS BEGIN CASE ADDR IS WHEN "000000" => DATAOUT<="11010010001111110110000000" WHEN "000001" => DATAOUT<="10001010001111111000000000" WHEN "000010" => DATAOUT<="10001110100111111100000000" WHEN "000011" => DATAOUT<="10000110011111111100000000" WHEN "000100" => DATAOUT<="10000010001111111001000000" WHEN "000101" => DATAOUT<="10001010001011111100000000" WHEN "000110" => DATAOUT<="01000010001111111000000000" WHEN "000111" => DATAOUT<="10001111000111111100000000" WHEN "001000" => DATAOUT<="10001011010111111100000000" WHEN "001001" => DATAOUT<="10000000001101111100000000" WHEN "010000" => DATAOUT<="01000010001111111000000000" WHEN OTHERS => DATAOUT<="10000010001111111100000000" END CASE; UA(5 DOWNTO 0)<=DATAOUT(5 DOWNTO 0); O(19 DOWNTO 0)<=DATAOUT(25 DOWNTO 6); END PROCESS;END A;LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY F3 IS PORT( D:IN STD_LOGIC_VECTOR(3 DOWNTO 0); UA3,UA2,UA1,UA0: OUT STD_LOGIC );END F3;ARCHITECTURE A OF F3 ISBEGIN UA3<=D(3); UA2<=D(2); UA1<=D(1); UA0<=D(0);END A;LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_ARITH.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY MCOMMAND ISPORT( T2,T3,T4:IN STD_LOGIC; D:IN STD_LOGIC_VECTOR(19 DOWNTO 0); LOAD,LDPC,LDAR,LDIR,LDRI,LDPSW,RS_B,S2,S1,S0:OUT STD_LOGIC; ALU_B,SW_B,LED_B,RD_D,CS_D,RAM_B,CS_I,ADDR_B,P1,P2:OUT STD_LOGIC );END MCOMMAND;ARCHITECTURE A OF MCOMMAND ISSIGNAL DATAOUT:STD_LOGIC_VECTOR(19 DOWNTO 0);BEGIN PROCESS(T2) BEGIN IF(T2EVENT AND T2=1) THEN DATAOUT(19 DOWNTO 0)<=D(19 DOWNTO 0); END IF; LOAD<=DATAOUT(19); LDPC<=DATAOUT(18) AND T4; LDAR<=DATAOUT(17) AND T3; LDIR<=DATAOUT(16) AND T3; LDRI<=DATAOUT(15) AND T4; LDPSW<=DATAOUT(14) AND T4; RS_B<=DATAOUT(13); S2<=DATAOUT(12); S1<=DATAOUT(11); S0<=DATAOUT(10); ALU_B<=DATAOUT(9); SW_B<=DATAOUT(8); LED_B<=DATAOUT(7); RD_D<=NOT(NOT DATAOUT(6) AND (T2 OR T3); CS_D<=NOT(NOT DATAOUT(5) AND T3); RAM_B<=DATAOUT(4); CS_I<=DATAOUT(3); ADDR_B<=DATAOUT(2); P1<=DATAOUT(1); P2<=DATAOUT(0); END PROCESS;END A; Top頂層圖的：MUX3功能表輸入 輸出SW-B CS ID7.0 N17.0 N27.0 EW7.00 X X X X IN7.01 0 X X X N27.01 1 X X X N17.0LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY MUX3 ISPORT(ID:IN STD_LOGIC_VECTOR(7 DOWNTO 0);SW_B,CS:IN STD_LOGIC;N1,N2:IN STD_LOGIC_VECTOR(7 DOWNTO 0);EW:OUT STD_LOGIC_VECTOR(7 DOWNTO 0);END MUX3;ARCHITECTURE A OF MUX3 ISBEGIN PROCESS(SW_B,CS) BEGIN IF(SW_B=0) THEN EW<=ID; ELSIF(CS=0)THEN EW<=N2; ELSEEW<=N1;END IF; END PROCESS;END A;ROM功能CS=1,不選擇CS=0，讀LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_ARITH.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY ROM IS PORT(DOUT:OUT STD_LOGIC_VECTOR(15 DOWNTO 0);ADDR:IN STD_LOGIC_VECTOR(7 DOWNTO 0);CS_I:IN STD_LOGIC);END ROM;ARCHITECTURE A OF ROM ISBEGINDOUT<="0001000000000000" WHEN ADDR="00000000" AND CS_I=0 ELSE "0001000111111111" WHEN ADDR="00000001" AND CS_I=0 ELSE "0001001000000101" WHEN ADDR="00000010" AND CS_I=0 ELSE "0010000000000000" WHEN ADDR="00000011" AND CS_I=0 ELSE "0011100000000000" WHEN ADDR="00000100" AND CS_I=0 ELSE "0100000000001100" WHEN ADDR="00000101" AND CS_I=0 ELSE "0101001100000000" WHEN ADDR="00000110" AND CS_I=0 ELSE "0011110100000000" WHEN ADDR="00000111" AND CS_I=0 ELSE "0100000000001010" WHEN ADDR="00001000" AND CS_I=0 ELSE "0110000000000011" WHEN ADDR="00001001" AND CS_I=0 ELSE "1000110100000000" WHEN ADDR="00001010" AND CS_I=0 ELSE "0110000000000011" WHEN ADDR="00001011" AND CS_I=0 ELSE "0111000100000000" WHEN ADDR="00001100" AND CS_I=0 ELSE "0010000100000000" WHEN ADDR="00001101" AND CS_I=0 ELSE "1001010000000000" WHEN ADDR="00001110" AND CS_I=0 ELSE "0000000000000000"END A;LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_ARITH.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY COUNTER ISPORT( CLK,CLR: IN STD_LOGIC; T2,T3,T4: OUT STD_LOGIC );END COUNTER;ARCHITECTURE A OF COUNTER ISSIGNAL X:STD_LOGIC_VECTOR(1 DOWNTO 0):="00"BEGIN PROCESS(CLK,CLR) BEGIN IF(CLR=0) THEN T2<=0; T3<=0; T4<=0; X<="00" ELSIF(CLKEVENT AND CLK=1) THEN X<=X+1; T2<=(NOT X(1)AND X(0); T3<=X(1) AND(NOT X(0); T4<=X(1) AND X(0); END IF; END PROCESS;END A;LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY LS273 ISPORT( D: IN STD_LOGIC_VECTOR(7 DOWNTO 0); CLK: IN STD_LOGIC; Q: OUT STD_LOGIC_VECTOR(7 DOWNTO 0) );END LS273; ARCHITECTURE A OF LS273 ISBEGIN PROCESS(CLK) BEGIN IF(CLKEVENT AND CLK=1) THEN Q<=D; END IF; END PROCESS;END A;ALU功能表S2 S1 S0 功能0 0 0 ADD,鎖存CF，ZF0 1 1 CMP(比較指令)0 1 0 INC（加1指令）1 1 0 NOT(取反指令)1 0 1 MOV1 (Rs) (Rd)LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_ARITH.ALL;USE IEEE.STD_LOGIC_UNSIGNED.all;ENTITY ALU ISPORT( X: IN STD_LOGIC_VECTOR(7 DOWNTO 0); Y: IN STD_LOGIC_VECTOR(7 DOWNTO 0); S2,S1,S0: IN STD_LOGIC; ALUOUT: OUT STD_LOGIC_VECTOR(7 DOWNTO 0) ; CF,ZF: OUT STD_LOGIC );END ALU;ARCHITECTURE A OF ALU ISSIGNAL AA,BB,TEMP:STD_LOGIC_VECTOR(8 DOWNTO 0);SIGNAL TEMP1:STD_LOGIC_VECTOR(7 DOWNTO 0);BEGIN PROCESSBEGIN IF(S2=0 AND S1=0 AND S0=0) THEN-ADD AA<=0&X; BB<=0&Y; TEMP<=AA+BB;ALUOUT<=TEMP(7 DOWNTO 0); CF<=TEMP(8); IF (TEMP="100000000" OR TEMP="000000000") THEN ZF<=1; ELSE ZF<=0; END IF;ELSIF(S2=0 AND S1=0 AND S0=1) THEN -CMP(SUB) AA<=0&X; BB<=0&Y; TEMP<=AA-BB;ALUOUT<=TEMP(7 DOWNTO 0);TEMP1<=TEMP(7 DOWNTO 0); CF<=TEMP1(7); IF (TEMP1="00000000") THEN ZF<=1; ELSE ZF<=0; END IF; ELSIF(S2=0 AND S1=1 AND S0=0) THEN -INC AA<=0&Y; TEMP<=AA+1; ALUOUT<=TEMP(7 DOWNTO 0); CF<=TEMP(8); IF (TEMP="100000000") THEN ZF<=1; ELSE ZF<=0; END IF; ELSIF(S2=0 AND S1=1 AND S0=1) THEN -DEC AA<=0&Y; TEMP<=AA-1; ALUOUT<=TEMP(7 DOWNTO 0); CF<=TEMP(8); IF (TEMP="000000000") THEN ZF<=1; ELSE ZF<=0; END IF; ELSIF(S2=1 AND S1=0 AND S0=0) THEN -NOT TEMP1<=NOT Y; ALUOUT<=TEMP1; ELSIF(S2=1 AND S1=0 AND S0=1) THEN -MOV1 ALUOUT<=X; ELSIF(S2=1 AND S1=1 AND S0=0) THEN -Rd->BUS ALUOUT<=Y;ELSE ALUOUT<="00000000" ; CF<=0; ZF<=0; END IF; END PROCESS;END A;PC功能CLR LOAD LDPC 功能0 X X 將PC清01 0 BUSPC1 1 0 不裝入，也不計(jì)數(shù)1 1 PC+1LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_ARITH.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY PC ISPORT( LOAD,LDPC,CLR: IN STD_LOGIC; D: IN STD_LOGIC_VECTOR(7 DOWNTO 0); Q: OUT STD_LOGIC_VECTOR(7 DOWNTO 0) );END PC;ARCHITECTURE A OF PC ISSIGNAL QOUT: STD_LOGIC_VECTOR(7 DOWNTO 0);BEGIN PROCESS(LDPC,CLR,LOAD) BEGIN IF(CLR=0) THEN QOUT<="00000000" ELSIF(LDPCEVENT AND LDPC=1) THEN IF(LOAD=0) THEN QOUT<=D; -BUS->PC ELSE QOUT<=QOUT+1; -PC+1 END IF; END IF; END PROCESS; Q<=QOUT;END A;FEN2功能表輸入 輸出WR LED-B X7.0 W17.0 W27.00 0 X X7.0 其他取值 X X7.0LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY FEN2 ISPORT(LED_B:IN STD_LOGIC;DBUS:IN STD_LOGIC_VECTOR(7 DOWNTO 0);FENOUT,OUTBUS:OUT STD_LOGIC_VECTOR(7 DOWNTO 0);END FEN2;ARCHITECTURE A OF FEN2 ISBEGIN PROCESS BEGIN IF(LED_B=0) THEN OUTBUS<=DBUS; ELSE FENOUT<=DBUS; END IF; END PROCESS;END A;第24頁