VerilogHDL語言,華中科技大學(xué)計算機(jī)科學(xué)與技術(shù)學(xué)院,主講：胡迪青Email:hudq024QQ:121374333,2,簡單數(shù)字電路設(shè)計,3,設(shè)計驗證與仿真,VerilogHDL不僅提供描述設(shè)計的能力，而且提供對激勵、控制、存儲響應(yīng)和設(shè)計驗證的建模能力。激勵和控制可用初始化語句產(chǎn)生。驗證運(yùn)行過程中的響應(yīng)可以作為“變化時保存”或作為選通的數(shù)據(jù)存儲。最后，設(shè)計驗證可以通過在初始化語句中寫入相應(yīng)的語句自動與期望的響應(yīng)值比較完成。要測試一個設(shè)計塊是否正確，就要用Verilog再寫一個測試模塊。這個測試模塊應(yīng)包括以下三個方面的內(nèi)容：測試模塊中要調(diào)用到設(shè)計塊，只有這樣才能對它進(jìn)行測試；測試模塊中應(yīng)包含測試的激勵信號源；測試模塊能夠?qū)嵤敵鲂盘柕臋z測，并報告檢測結(jié)果。,4,Simulating/ValidatingHDL,Thesadtruth10%design,90%validationIfyoudoitrightyouwillspend9Xmoretimetesting/validatingadesignthandesigningit.,5,TestbenchExample(contrivedbutvalid),moduletest_and;integerfile,i,code;rega,b,expect,clock;wireout;parametercycle=20;and#4a0(out,a,b);/Circuitundertestinitialbegin:file_blockclock=0;file=$fopen("compare.txt",“r”);for(i=0;i<4;i=i+1)begin(posedgeclock)/Readstimulusonrisingclockcode=$fscanf(file,"%b%b%bn",a,b,expect);#(cycle-1)/Comparejustbeforeendofcycleif(expect!=out)$strobe("%d%b%b%b%b",$time,a,b,expect,out);end/for$fclose(file);$stop;end/initialalways#(cycle/2)clock=clock;/Clockgeneratorendmodule,6,組合邏輯設(shè)計,組合邏輯電路可以有若個輸入變量和若干個輸出變量，其每個輸出變量是其輸入的邏輯函數(shù)，其每個時刻的輸出變量的狀態(tài)僅與當(dāng)時的輸入變量的狀態(tài)有關(guān)，與本輸出的原來狀態(tài)及輸入的原狀態(tài)無關(guān)，也就是輸入狀態(tài)的變化立即反映在輸出狀態(tài)的變化。邏輯電路的各種運(yùn)算可以用布爾代數(shù)來描述狄摩根定律利用狄摩根（DeMorgan）定律可以將積之和形式的電路轉(zhuǎn)換為和之積形式的電路，或反之。,7,組合邏輯的三種通用表示方法結(jié)構(gòu)化（即門級）原理圖真值表布爾方程式實例：半加器,8,CombinationalCircuitsComponentInstantiations,CircuitAconnectionofmodules,AlsoknownasstructureAcircuitisasecondwaytodescribea,module,vs.usinganalwaysprocedure,asearlier,InstanceAnoccurrenceofamoduleinacircuitMaybemultipleinstancesofamodule,e.g.,Carsmodules:tires,engine,windows,etc.,with4tireinstances,1engineinstance,6windowinstances,etc.,9,CombinationalCircuitsModuleInstantiations,10,CombinationalCircuitsModuleInstantiations,11,CombinationalCircuitsModuleInstantiations,12,CombinationalCircuitStructureSimulatinggtheCircuit,SametestbenchformatforBeltWarnmoduleasforearlierAnd2module,13,CombinationalCircuitStructureSimulatinggtheCircuit,14,CombinationalCircuitStructureSimulatinggtheCircuit,timescale1ns/1nsmoduleTestbench();regK_s,P_s,S_s;wireW_s;BeltWarnCompToTest(K_s,P_s,S_s,W_s);initialbegin,MoreontestbenchesNotethatasinglemoduleinstantiationstatementusedregandwiredeclarations(K_s,P_s,S_s,W_s)usedbecauseprocedurecannotaccessinstantiatedmodules,<=0;S_sP_s<=1;P_s<=1;P_s<=1;,<=0;S_s<=0;S_s<=0;S_s<=1;,K_s<=0;P_s#10K_s<=0;#10K_s<=1;#10K_s<=1;endendmodule,portsdirectlyInputsdeclaredasregssocanassignvalues(whichareheldbetweenassignments)Notemoduleinstantiationstatement,andprocedurecanbothappearinonemodule,15,CombinationalBehaviortoStructure,16,CombinationalBehaviortoStructureAlwaysProcedureswithAssignmentStatements,17,CombinationalBehaviortoStructureProcedureswithAssignmentStatements,ProceduralassignmentstatementAssignsvaluetovariableRightsidemaybeexpressionofoperators,timescale1ns/1nsmoduleBeltWarn(K,P,S,W);inputK,P,S;outputW;regW;,Built-inbitoperatorsinclude,end,18,CombinationalBehaviortoStructureProcedureswithAssignmentStatements,Proceduremayhavemultipleassignmentstatements,timescale1ns/1nsmoduleTwoOutputEx(A,B,C,F,G);,inputA,B,C;outputFF,G;regF,G;always(A,B,C)beginF<=(Bendendmodule,19,CombinationalBehaviortoStructureProcedureswithIf-ElseStatements,Processmayuseif-elsestatements(a.k.a.conditionalstatements),if(expression)Ifexpressionistrue(evaluatestononzerovalue),executecorrespondingstatement(s)Iffalse(evaluatesto0),executeelsessstatement(elsepartisoptional)Exampleshowsuseofoperator=,timescale1ns/1nsmoduleBeltWarn(K,P,S,W);inputK,P,S;outputW;regW;always(K,P,S)beginif(Kelse,W<=0;,logicalequality,returnstrue/false(actually,returns1or0),endendmodule,Trueisnonzerovalue,falseiszero,20,CombinationalBehaviortoStructureProcedureswithIf-ElseStatements,Morethantwopossibilities,Handledbystringingif-elsestatementstogetherKnownasif-else-ifconstruct,Example:4x1muxbehavior,timescale1ns/1nsmoduleMux4(I3,I2,I1,I0,S1,S0,D);inputI3,I2,I1,I0;,inputS1,S0;outputD;,SupposeS1S0changeto01,SupposeS1S0changeto01ifsexpressionisfalseelsesstatementexecutes,whichisanifstatementwhoseexpressionistrue,regD;always(I3,I2,I1,I0,S1,S0)beginif(S1=0,elseif(S1=1,Note:Thefollowingindentationshowsifstatementnesting,butisunconventional:if(S1=0else,if(S1=0else,values,returnstrue/false),21,CombinationalBehaviortoStructureProcedureswithIf-ElseStatements,22,CombinationalBehaviortoStructure,23,CombinationalBehaviortoStructureCommonPitfallMissingInputsfromEventControlExpression,24,CombinationalBehaviortoStructureCommonPitfallMissingInputsfromEventControlExpression,Verilogprovidesmechanismtohelpavoidthispitfall,*impliciteventcontrolexpressionAutomaticallyaddsallnetsandvariablesthatarereadbythecontrolledstatementorstatementgroupThus,*inexampleisequivalentto(S1,S0,I0,I1,I2,I3),timescale1ns/1nsmoduleMux4(I3,I2,I1,I0,S1,S0,D);inputI3,I2,I1,I0;inputS1,S0;outputD;regD;,(*)alsoequivalentalways*beginif(S1=0endendmodule,25,CombinationalBehaviortoStructureCommonPitfallOutputnotAssignedonEveryPass,26,CombinationalBehaviortoStructureCommonPitfallOutputnotAssignedonEveryPass,Samepitfalloftenoccursduetonotconsideringallpossibleinputcombinationsif(I1=0endelseif(I1=1D2<=1;,D1<=0;D0<=0;,Last"else"missing,sonotall,end,inputcombinationsarecovered(i.e.,I1I0=11notcovered),